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databrief january 2006 1/11 rev. 2 ? STD2000 single-chip worldwide idtv processor dual-channel high definition video processor up to 12-bit video processing 3d digital luma/chroma noise reduction 3d motion adaptive pixel-based advanced deinterlacing with diagonal compensation contour sensitive de-interlacing csdi? flexible h/v scaling engine with multi window management capabilities image quality improvement engine for crystal clear and crisp pictures dual digital chroma decoder (pal/secam/ntsc) with 3d/2d comb filter and dual vbi data slicer powerful 32-bit risc st40 cpu (266 mhz, 480 mips) dual transport stream demux with des, dvb and multi2 descrambler dual dvb-ci/one cablecard? interface mp@ml dual channel or mp@hl single channel mpeg-2 video decoder 24-bit audio dsp core, mpeg-1 (layers 1, 2 & 3), mpeg2, dolby ? digital decoder gamma 2d graphics engine for middleware graphics and on-screen display auxiliary video/graphics sub-system for monitor output exhaustive set of peripherals for dtv chassis control ddr333 unified memory interface (lmi) programmable external memory interface (emi) crt and flat panel display video outputs 27 mhz crystal oscillator id video display pipeline (tnr, dei, scaling, iqi) hd video display pipeline (tnr, dei, scaling, iqi) compositor st bus on-chip interconnect dual transport demux mpeg-2 mp@hl mp@mlx2 video dual c.i. / one cablecard? chassis control timebase clock generator lmi emi 266 mhz 480 mips 16k - i, 32k-d st40 cpu decoder h/v src nor flash ddr sdram sd/id analog video mpeg-2 audio & video sd/hd digital video display lcd pdp peripherals vcr dual ddec 3d comb dlp crt dvd display driver digital encoder recorder vbi dma gamma 2d graphics digital digital mpeg 1&2 dolby digital audio dsp decoder mp3 audio in audio out graphics
STD2000 2/11 dual channel video input processor analog video inputs cvbs, y/c, 1h/2h/2.14h yprpb, 1h/2h rgb analog inputs digital video inputs d1/hd digital video input (ccir 601-656 / smpte 274m, smpte 296m, smpte 260m) ycl digital video input (proprietary port; ycrcb-4:2:2, 2h for off-chip motion- compensated video processing) rgb to ycrcb 4:2:2 conversion analog video pre-processing dual digital chroma decoder (pal/ntsc/secam) 3d comb filter support on one channel, adaptative 4h/2d comb filter on second channel dual vbi data slicer for teletext, cc, wss and other systems 3:2/2:2 pulldown, video/movie and scene change detection 3d digital luma and chroma motion adaptive noise reduction automatic letterbox detection dual channel high definition video processor image processing 24, 25, 30, 50, 60 to 50, 60, 75, 100, 120 hz field up-rate conversion 3d motion-adaptive pixel-based advanced deinterlacing with diagonal compensation (csdi?: contour sensitive desinterlacer) image quality improvements lti and cti contrast enhancer: black-white stretch blue stretch green boost, auto-flesh and tint control peaking: adaptive peaking and coring video scaling & composition horizontal/vertical format conversion support of 4:3 and 16:9 display aspect ratios zoom in or zoom out (x and y independent linear factors from x0.25 to x4) panoramic mode h or v crop and independent rescaling compositor supporting monochrome and graphics planes video two-channel hd processing for: pip/pop, picture and picture (perfect pap), picture in graphic (pig) video output control color space translator (conversion to ycrcb 4:4:4 or rgb coding) gamma correction with programmable any- curve correction perfect color engine (spatio-temporal dithering down to 4-to-8 bits) rgb 3x10-bit digital output to flat panel or dmd rgb or yuv analog outputs color warping for color gammut correction cpu sub-system 32-bit risc st40 cpu (266 mhz, 480mips) 16 kbytes i-cache and 32 kbytes d-cache ram floating point unit (fpu) memory management unit (mmu) on-chip memory (64 kbytes sram) services test access port and its link (jtag based) diagnostic controller unit (for low intrusion, real-time debugging) advanced user debug support system bus analyzer (sbag) dual transport stream processor dual transport stream demux des, dvb and multi2 descramblers dual transport processing: dvb or atsc (iso/iec 13818-x and a53) dvb-ci interface (dual slot support) cablecard? interface (single slot support)
3/11 STD2000 mpeg2 digital video decoder mpeg2 video (iso/iec 13818-2, atsc-a54) mp@ml dual-channel decode or mp@hl single-channel decode data extraction (closed caption,...) digital audio decoder 24-bit audio dsp core (with embedded software & patch ram) mpeg1 (layers 1, 2 & 3), mpeg2, dolby? digital / atsc-a52 lt/rt downmix for standard stereo digital outputs triple i2s channel outputs one pcm/stream or i2s input (s/pdif external receiver or hdmi) s/pdif digital output (iec60958 and iec61937) gamma 2d graphic processor full screen or windowed bitmap area argb-4444 graphics plane in mixed mode 2d-graphics hardware accelerator gfx/video programmable alpha-blending background color plane horizontal and/or vertical scrolling, controlled by software auxiliary video/graphics processor on-chip pal/ntsc/secam encoder for monitor output encoding of teletext, wss, vps or closed caption graphics plane for optional subtitle support macrovision copy protection (factory disable option) dtv chassis control tw o ua rt s one smartcard interface two i2c (2 channels each) four-channel pwm with input capture and compare real-time clock and watchdog timer infrared receiver/transmitter 10-bit, 8-channel low-speed a/d converter 8 external interrupt channels with interrupt level controller more than 56 general purpose ios low-power mode and wake-up controller interfaces local memory interface (lmi) 64-bit, dual-port ddr memory interface 16- and 32-bit ddr-sdram device support up to 166 mhz support support devices of up to 512 mbits programmable external memory interface (emi) 16-bit/8-bit external memory interface for supporting flash and optional peripherals support nor flash devices of up to 256 mbits 6 separately configurable banks support for external memory-mapped ics or sub-systems fdp and crt video outputs rgb 3x10-bit digital output to flat panel or dmd rgb or yuv analog outputs for crt
general information STD2000 4/11 1 general information 1.1 introduction the STD2000 is a highly-integrated, high performance system-on-chip idtv processor that combines set-top box decoding facility with a powerful tv processor. a dual-channel pip/pap video processor supports high definition formats. its advanced integration drastically reduces integrated digital tv bom costs by removing redundancy between analog and digital source video processing. compliant with worldwide standards such as atsc, dvb-t, isdb-t and the chinese digital terrestrial standard, the STD2000 also includes a built-in cablecard? interface for us opencable? specifications and a dual dvb-ci interface for european dvb-t specifications. 1.2 typical applications typical applications for the STD2000 system-on-chip are illustrated in the following diagrams: figure 1: us lcd digital cable ready hdtv
5/11 STD2000 general information figure 2: china crt digital cable hdtv figure 3: europe lcd idtv ca chinese c.i. optional
STD2000 pin list STD2000 6/11 2 STD2000 pin list 2.1 general package information the STD2000 is delivered in a 745-ball bga package. table 1: bga package information package type mcm-bga body size 40 x 40 mm ball count 745 balls ball pitch 1.27 mm ball matrix 31 x 31 (5-row perimeter) balls center matrix 15 x 15 balls figure 4: STD2000 package overview a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 c29 c30 c31 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 e19 e20 e21 e22 e23 e24 e25 e26 e27 e28 e29 e30 e31 f1 f2 f3 f4 f5 f27 f28 f29 f30 f31 g1 g2 g3 g4 g5 g27 g28 g29 g30 g31 h1 h2 h3 h4 h5 h27 h28 h29 h30 h31 j1 j2 j3 j4 j5 j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j20 j21 j22 j23 j27 j28 j29 j30 j31 k1 k2 k3 k4 k5 k9 k10 k11 k12 k13 k14 k15 k16 k17 k18 k19 k20 k21 k22 k23 k27 k28 k29 k30 k31 feed_back 2.5v l1 l2 l3 l4 l5 l9 l10 l11 l12 l13 l14 l15 l16 l17 l18 l19 l20 l21 l22 l23 l27 l28 l29 l30 l31 m1 m2 m3 m4 m5 m9 m10 m11 m12 m13 m14 m15 m16 m17 m18 m19 m20 m21 m22 m23 m27 m28 m29 m30 m31 n1 n2 n3 n4 n5 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n22 n23 n27 n28 n29 n30 n31 p1 p2 p3 p4 p5 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p27 p28 p29 p30 p31 r1 r2 r3 r4 r5 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r27 r28 r29 r30 r31 t1 t2 t3 t4 t5 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t27 t28 t29 t30 t31 u1 u2 u3 u4 u5 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u27 u28 u29 u30 u31 v1 v2 v3 v4 v5 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v27 v28 v29 v30 v31 w1 w2 w3 w4 w5 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 w21 w22 w23 w27 w28 w29 w30 w31 y1 y2 y3 y4 y5 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 y27 y28 y29 y30 y31 aa1 aa2 aa3 aa4 aa5 aa9 aa10 aa11 aa12 aa13 aa14 aa15 aa16 aa17 aa18 aa19 aa20 aa21 aa22 aa23 aa27 aa28 aa29 aa30 aa31 audio ab1 ab2 ab3 ab4 ab5 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 ab19 ab20 ab21 ab22 ab23 ab27 ab28 ab29 ab30 ab31 ac1 ac2 ac3 ac4 ac5 ac9 ac10 ac11 ac12 ac13 ac14 ac15 ac16 ac17 ac18 ac19 ac20 ac21 ac22 ac23 ac27 ac28 ac29 ac30 ac31 ad1 ad2 ad3 ad4 ad5 ad27 ad28 ad29 ad30 ad31 ae1 ae2 ae3 ae4 ae5 ae27 ae28 ae29 ae30 ae31 af1 af2 af3 af4 af5 af27 af28 af29 af30 af31 ag1 ag2 ag3 ag4 ag5 ag6 ag7 ag8 ag9 ag10 ag11 ag12 ag13 ag14 ag15 ag16 ag17 ag18 ag19 ag20 ag21 ag22 ag23 ag24 ag25 ag26 ag27 ag28 ag29 ag30 ag31 ah1 ah2 ah3 ah4 ah5 ah6 ah7 ah8 ah9 ah10 ah11 ah12 ah13 ah14 ah15 ah16 ah17 ah18 ah19 ah20 ah21 ah22 ah23 ah24 ah25 ah26 ah27 ah28 ah29 ah30 ah31 aj1 aj2 aj3 aj4 aj5 aj6 aj7 aj8 aj9 aj10 aj11 aj12 aj13 aj14 aj15 aj16 aj17 aj18 aj19 aj20 aj21 aj22 aj23 aj24 aj25 aj26 aj27 aj28 aj29 aj30 aj31 ak1 ak2 ak3 ak4 ak5 ak6 ak7 ak8 ak9 ak10 ak11 ak12 ak13 ak14 ak15 ak16 ak17 ak18 ak19 ak20 ak21 ak22 ak23 ak24 ak25 ak26 ak27 ak28 ak29 ak30 ak31 al1 al2 al3 al4 al5 al6 al7 al8 al9 al10 al11 al12 al13 al14 al15 al16 al17 al18 al19 al20 al21 al22 al23 al24 al25 al26 al27 al28 al29 al30 al31 ycl system 2 analog in ref supply 3.3va supply 1.8va (4) supply 1.8v (4) analog out ref coms supply 1.0v denc analog in ts2 in pios scan analog out ts1 in coms audio system1 denc ref d1 in 3.3v supply (4) power supply feedback 2 2.5v analog supply (6) test lmi 1 lmi 2 emi 2.5v supply 3.3v supply (nc) test ci d1 out
7/11 STD2000 STD2000 pin list 2.2 ballout description figure 5: ballout information (part 1) ball signal ball signal ball signal ball signal ball signal ball signal ball signal ball signal a1 ddr2_cas d1 ddr2_clk j2 gnd m23 gnd t16 gnd y9 ms_tdi ac30 ci1_mdo0 ah31 ts2_din1 a2 ddr2_ba1 d2 ddr2_ad12 j3 ddr2_dqs3 m27 vdd33p t17 gnd y10 gnd ac31 ci2_mdo1 aj1 fpd_b5 a3 ddr2_ad3 d3 ddr2_ad9 j4 ddr2_d25 m28 (nc-9) t18 gnd y11 gnd ad1 mafeif_fsi aj2 fpd_b4 a4 ddr2_ba0 d4 ddr2_ad1 j5 ddr2_d24 m29 (nc-10) t19 gnd y12 gnd ad2 sc_clk aj3 fpd_b3 a5 ddr2_d13 d5 ddr2_d15 j9 gnd m30 (nc-8) t20 gnd y13 gnd ad3 sc_data aj4 fpd_g7 a6 ddr2_d8 d6 ddr2_d10 j10 gnd m31 (nc-7) t21 gnd y14 gnd ad4 sc_rst aj5 fpd_g4 a7 ddr2_dqs0 d7 ddr2_dm1 j11 gnd n1 sba_sync t22 gnd y15 gnd ad5 sc_cmd_vcc aj6 fpd_g0 a8 ddr2_d4 d8 ddr2_d6 j12 gnd n2 aud_ck t23 gnd y16 gnd ad27 ci1_ce1_pod_ce2 aj7 fpd_r6 a9 ddr2_d0 d9 ddr2_d2 j13 gnd n3 aud_dat2 t27 vdd33p y17 gnd ad28 ci_oe aj8 fpd_r2 a10 ddr1_d28 d10 ddr1_d30 j14 gnd n4 aud_dat0 t28 ci2_mdi0 y18 gnd ad29 ci2_ce1_pod_ce1 aj9 fpd_de_pwm3 a11 ddr1_d24 d11 ddr1_d26 j15 gnd n5 aud_dat1 t29 ci1_mistrt y19 gnd ad30 ci_iord aj10 houta_pwm2 a12 ddr1_dm2 d12 ddr1_dqs3 j16 ddr_rext n9 vpp t30 ci1_mdi0 y20 gnd ad31 ci_iowr aj11 hclkvbk a13 ddr1_d21 d13 ddr1_d23 j17 gnd n10 gnd t31 ci2_mdi1 y21 gnd ae1 sc_detect aj12 rout a14 ddr1_d17 d14 ddr1_d19 j18 gnd n11 gnd u1 ycl_val y22 gnd ae2 cda_req_rxd aj13 svm a15 ddr1_ad6 d15 ddr1_d16 j19 gnd n12 gnd u2 ycl_vsync y23 gnd ae3 cda_dat_cts aj14 cvbs2_y2_n a16 ddr1_ad8 d16 ddr1_cke j20 gnd n13 gnd u3 d1o_bi_cbi_2 y27 gnd ae4 cda_ck_txd aj15 r1_c1_pr1_p a17 ddr1_clk d17 ddr1_ad9 j21 gnd n14 gnd u4 d1o_bi_cbi_0 y28 ci1_moval ae5 cda_dval_rts aj16 vsync a18 ddr1_ad5 d18 ddr1_cas j22 gnd n15 gnd u5 d1o_bi_cbi_1 y29 ci2_moval ae27 ci2_mdi6 aj17 denc_y a19 ddr1_cs d19 ddr1_ad0 j23 gnd n16 gnd u9 vdd10p y30 ci2_mdo5 ae28 ci1_mdi6 aj18 sscg_cki a20 ddr1_ad3 d20 ddr1_ad10 j27 vdd33p n17 gnd u10 gnd y31 ci1_mdo5 ae29 ci1_mdi5 aj19 xtalout a21 ddr1_ras d21 ddr1_d15 j28 emi_oe n18 gnd u11 gnd aa1 d1i_hd_ck ae30 ci2_mdi7 aj20 clkxtp a22 ddr1_d14 d22 ddr1_d12 j29 emi_d0 n19 gnd u12 gnd aa2 d1i_hd_hsync ae31 ci1_mdi7 aj21 i2so_dat2 a23 ddr1_d10 d23 ddr1_d8 j30 emi_fla_csn n20 gnd u13 gnd aa3 i2si_sck af1 int0 aj22 i2so_mck a24 ddr1_dm1 d24 ddr1_dqs0 j31 emi_a0 n21 gnd u14 gnd aa4 d1i_hd_vsync af2 int1 aj23 int3 a25 ddr1_d7 d25 ddr1_d5 k1 ddr2_d31 n22 gnd u15 gnd aa5 i2si_lrck af3 gpio2 aj24 ad4 a26 ddr1_d3 d26 ddr1_d1 k2 ddr2_d30 n23 gnd u16 gnd aa9 ms_tms af4 gpio0 aj25 timer0_blast_out a27 emi_a2 d27 emi_a4 k3 ddr2_d27 n27 vdd33p u17 gnd aa10 ms_tstrstn af5 gpio1 aj26 sda2 a28 emi_a6 d28 emi_a13 k4 ddr2_d29 n28 (nc-5) u18 gnd aa11 gnd af27 ci1_mdi3 aj27 ts1_din6 a29 emi_a18 d29 emi_a12 k5 ddr2_d28 n29 (nc-6) u19 gnd aa12 ms_scanmode af28 ci2_mdi4 aj28 ts1_din2 a30 emi_r/wn d30 emi_a14 k9 n 30 (nc-4) u20 gnd aa13 ms_tstmode af29 ci2_mdi3 aj29 ts1_ck a31 emi_a20 d31 emi_a15 k10 gnd n31 (nc-3) u21 gnd aa14 gnd af30 ci1_mdi4 aj30 ts2_din5 b1 ddr2_vref e1 ddr2_ad11 k11 gnd p1 sba_ck u22 gnd aa15 tst_afe0 af31 ci2_mdi5 aj31 ts2_din4 b2 ddr2_cs e2 gnd k12 gnd p2 sba_dat0 u23 denc_vref aa16 tst_afe1 ag1 timer1_pwm4 ak1 fpd_b2 b3 ddr2_ad2 e3 ddr2_clkn k13 gnd p3 sba_dat3 u27 ci1_wait aa17 tst_afe2 ag2 v10_reg_out ak2 fpd_b1 b4 ddr2_ad10 e4 ddr2_cke k14 gnd p4 sba_dat1 u28 ci2_mival aa18 tst_afe3 ag3 v18_reg_out ak3 fpd_g8 b5 ddr2_d14 e5 ddr2_we k15 gnd p5 sba_dat2 u29 ci2_wait aa19 gnd ag4 sda0 ak4 fpd_g6 b6 ddr2_d9 e6 ddr2_d11 k16 gnd p9 vdd10p u30 ci1_mival aa20 ms_tstck27 ag5 scl0 ak5 fpd_g2 b7 ddr2_dm0 e7 ddr2_dqs1 k17 gnd p10 gnd u31 ci2_mistrt_pod_oob_di aa21 ms_tstck54 ag6 vdd33s ak6 fpd_r8 b8 ddr2_d5 e8 vdd25p k18 gnd p11 gnd v1 d1o_bi_cbi_3 aa22 ms_tstck81 ag7 vdd33s ak7 fpd_r4 b9 ddr2_d1 e9 vdd25p k19 gnd p12 gnd v2 d1o_bi_cbi_4 aa23 gnd ag8 vdd33s ak8 fpd_r0 b10 ddr1_d29 e10 vdd25p k20 gnd p13 gnd v3 d1o_bi_cbi_7 aa27 ci2_ireq ag9 vdd33s ak9 fpd_ck1_vflyback b11 ddr1_d25 e11 vdd25p k21 gnd p14 gnd v4 d1o_bi_cbi_5 aa28 ci1_ireq ag10 iref_abe ak10 hs_out b12 ddr1_dm3 e12 vdd25p k22 gnd p15 gnd v5 d1o_bi_cbi_6 aa29 ci1_mdo3 ag11 gndref_abe ak11 dpc b13 ddr1_d22 e13 vdd25p k23 p16 gnd v9 vdd10p aa30 ci2_mdo4 ag12 vref_abe ak12 bout b14 ddr1_d18 e14 vdd25p k27 vdd33p p17 gnd v10 gnd aa31 ci1_mdo4 ag13 refp_afe_f ak13 c2_pr2_n b15 ddr1_ad4 e15 vdd25p k28 emi_csn0 p18 gnd v11 gnd ab1 i2si_mck ag14 refn_afe_f ak14 cvbs1_y1_pb2_n b16 ddr1_ad11 e16 vdd25p k29 emi_csn1 p19 gnd v12 gnd ab2 i2si_dat ag15 rref_afe ak15 g1_cvbs1p_y1p_p b17 ddr1_ad12 e17 vdd25p k30 emi_wait p20 gnd v13 gnd ab3 int7 ag16 rref_gnd_afe ak16 b1_pb1_n b18 ddr1_vref e18 vdd25p k31 (nc-15) p21 gnd v14 gnd ab4 sda1 ag17 vref_afe ak17 gnd b19 ddr1_ba1 e19 vdd25p l1 tdi p22 gnd v15 gnd ab5 scl1 ag18 refp_afe_s ak18 gnd b20 ddr1_ad1 e20 vdd25p l2 tdo p23 gnd v16 gnd ab9 ms_trst ag19 vcc10p ak19 gnd
STD2000 pin list STD2000 8/11 figure 6: ballout information (part 2) ball signal ball signal ball signal ball signal ball signal ball signal ball signal ball signal b21 ddr1_we e21 vdd25p l3 v25_reg_out p27 vdd33p v17 gnd ab10 gnd ag20 vcc10p ak20 gnd b22 ddr1_d13 e22 vdd25p l4 asebrk p28 (nc-1) v18 gnd ab11 gnd ag21 vcc25p ak21 gnd b23 ddr1_d9 e23 vdd25p l5 resetn p29 (nc-2) v19 gnd ab12 gnd ag22 i2so_sck ak22 i2so_dat0 b24 ddr1_dm0 e24 vdd25p l9 gnd p30 ci1_ci2_cs v20 gnd ab13 gnd ag23 int2 ak23 sda3 b25 ddr1_d6 e25 vdd25p l10 gnd p31 ci1_cd2 v21 gnd ab14 gnd ag24 ad3 ak24 ad1 b26 ddr1_d2 e26 ddr1_d0 l11 gnd r1 ycl_ri_cri_4 v22 gnd ab15 gnd ag25 ir ak25 ad6 b27 emi_a3 e27 emi_a22 l12 gnd r2 ycl_ri_cri_3 v23 denc_iref ab16 gnd ag26 int5 ak26 timer2_pwm5 b28 emi_a7 e28 emi_a16 l13 gnd r3 ycl_ri_cri_0 v27 ci2_mclki_pod_oob_ ab17 gnd ag27 ts1_din7 ak27 ts1_vdat b29 emi_a21 e29 emi_csn2 l14 gnd r4 ycl_ri_cri_2 v28 ci1_mclki_pod_a14 ab18 gnd ag28 ts2_ck ak28 ts1_din4 b30 emi_a19 e30 emi_d15 l15 gnd r5 ycl_ri_cri_1 v29 ci1_mdo7 ab19 gnd ag29 ts2_din0 ak29 ts1_din0 b31 emi_a8 e31 emi_d7 l16 gnd r9 vdd10p v30 ci2_reset ab20 gnd ag30 ci2_cd1 ak30 ts2_str c1 ddr2_ad7 f1 ddr2_d17 l17 gnd r10 gnd v31 ci1_reset ab21 gnd ag31 ci1_cd1 ak31 ts2_din6 c2 ddr2_ad5 f2 ddr2_d16 l18 gnd r11 gnd w1 d1o_ck ab22 gnd ah1 fpd_b9 al1 fpd_b0 c3 ddr2_ad0 f3 ddr2_ad8 l19 gnd r12 gnd w2 gnd ab23 gnd ah2 fpd_b8 al2 fpd_g9 c4 gnd f4 ddr2_ad4 l20 gnd r13 gnd w3 d1i_gi_yi82 ab27 ci2_mdo2 ah3 fpd_b6 al3 gnd c5 ddr2_ras f5 ddr2_ad6 l21 gnd r14 gnd w4 d1i_gi_yi_0 ab28 ci1_mdo2 ah4 fpd_b7 al4 fpd_g5 c6 ddr2_d12 f27 emi_d6 l22 gnd r15 gnd w5 d1i_gi_yi_1 ab29 ci1_mdo1 ah5 fpd_g3 al5 fpd_g1 c7 gnd f28 emi_d13 l23 gnd r16 gnd w9 vdd10p ab30 ci_we ah6 fpd_r9 al6 fpd_r7 c8 ddr2_d7 f29 emi_d14 l27 vdd33p r17 gnd w10 gnd ab31 ci2_mdo3 ah7 fpd_r5 al7 fpd_r3 c9 ddr2_d3 f30 emi_d5 l28 (nc-13) r18 gnd w11 gnd ac1 int6 ah8 fpd_r1 al8 fpd_gfx_pwm1 c10 ddr1_d31 f31 emi_d12 l29 (nc-14) r19 gnd w12 gnd ac2 mafeif_dout ah9 fpd_ck2_pwm0 al9 hdrive c11 ddr1_d27 g1 ddr2_d21 l30 (nc-12) r20 gnd w13 gnd ac3 mafeif_din ah10 vs_out al10 vmeas c12 gnd g2 ddr2_d20 l31 (nc-11) r21 gnd w14 gnd ac4 mafeif_hc1 ah11 bcl_saf al11 icath c13 ddr1_dqs2 g3 ddr2_d18 m1 aud_dat3 r22 gnd w15 gnd ac5 mafeif_sclk ah12 gout al12 blankout c14 ddr1_d20 g4 gnd m2 aud_sync r23 gnd w16 gnd ac9 ms_tck ah13 gnd al13 c2_pr2_p c15 gnd g5 ddr2_d19 m3 trst r27 vdd33p w17 gnd ac10 ms_tdo ah14 cvbs2_y2_p al14 cvbs1_y1_pb2_p c16 ddr1_clkn g27 vdd33p m4 tck r28 ci1_mdi2 w18 gnd ac11 vdd18s ah15 r1_c1_pr1_n al15 g1_cvbs1p_y1p_n c17 ddr1_ad7 g28 emi_d11 m5 tms r29 ci2_cd2 w19 gnd ac12 vdd18s ah16 fb al16 b1_pb1_p c18 gnd g29 emi_d4 m9 core_tst r30 ci2_mdi2 w20 gnd ac13 vdd18s ah17 denc_cvbs al17 hcsync c19 ddr1_ad2 g30 emi_d3 m10 gnd r31 ci1_mdi1 w21 gnd ac14 vdd18s ah18 refn_afe_s al18 denc_c c20 ddr1_ba0 g31 emi_d10 m11 gnd t1 ycl_ri_cri_5 w22 gnd ac15 vcc33s ah19 vcc10p al19 sscg_cko c21 gnd h1 ddr2_dm3 m12 gnd t2 ycl_ri_cri_6 w23 gnd ac16 vcc33s ah20 vcc25p al20 xtalin c22 ddr1_d11 h2 ddr2_dm2 m13 gnd t3 ycl_req w27 ci1_mclko ac17 vcc33s ah21 vcc25p al21 clkxtm c23 ddr1_dqs1 h3 ddr2_d22 m14 gnd t4 ycl_ri_cri_7 w28 ci2_mdo6 ac18 vcc18s ah22 i2so_lrck al22 i2so_dat1 c24 gnd h4 ddr2_dqs2 m15 gnd t5 ycl_ck w29 ci2_mclko_pod_rc74 ac19 vcc18s ah23 scl3 al23 spdif_out c25 ddr1_d4 h5 ddr2_d23 m16 gnd t9 vdd10p w30 ci1_mdo6 ac20 vcc18s ah24 ad2 al24 ad0 c26 emi_a1 h27 vdd33p m17 gnd t10 gnd w31 ci2_mdo7 ac21 vcc18s ah25 ad7 al25 ad5 c27 emi_a5 h28 emi_d9 m18 gnd t11 gnd y1 d1i_gi_yi_3 ac22 gnd ah26 timer3_int4 al26 gpio3 c28 emi_a17 h29 emi_d2 m19 gnd t12 gnd y2 d1i_gi_yi_4 ac23 gnd ah27 ts1_str al27 scl2 c29 emi_a9 h30 emi_d1 m20 gnd t13 gnd y3 d1i_gi_yi_7 ac27 ci1_mostrt ah28 ts1_din3 al28 ts1_din5 c30 emi_a10 h31 emi_d8 m21 gnd t14 gnd y4 d1i_gi_yi_5 ac28 ci2_mdo0_pod_a8 ah29 ts2_din3 al29 ts1_din1 c31 emi_a11 j1 ddr2_d26 m22 gnd t15 gnd y5 d1i_gi_yi_6 ac29 ci2_mostrt_pod_a9 ah30 ts2_din2 al30 ts2_vdat al31 ts2_din7
9/11 STD2000 package mechanical data 3 package mechanical data
revision history STD2000 10/11 4 revision history date revision changes 1-mar-2005 1 initial release 2-jan 2006 2 small changes applied to block diagram, features, figures 2 and 3.
11/11 STD2000 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwi se under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com notes:

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